1. Field of the Invention
This invention pertains to a semiconductor memory such as an EPROM (Erasable and Programmable Read Only Memory), and more particularly to improvement and compaction of a memory cell transistor of a ROM (Read Only Memory) for a non-volatile data storage provided in such a semiconductor memory.
2. Description of the Related Arts
EPROMs are widely known as typical non-volatile semiconductor memory devices.
Because EPROMs can hold stored data semipermanently as well as erase and overwrite them, they are used widely e.g. for firmware of systems having a lot of anticipated changes, systems on which programs are built upon by taking the compatibility with other systems into consideration, and systems in which many changes occur in the program specification.
A memory cell of an EPROM comprises a single transistor called a memory cell transistor.
FIGS. 1A, 1B and 1C are the top view and cutaways of an exemplary memory cell transistor of a conventional EPROM in a memory cell transistor.
More specifically, FIG. 1A shows a top view of a conventional memory cell transistor of an EPROM cell, FIG. 1B shows the A--A' cutaway of the memory cell transistor shown in FIG. 1A, and FIG. 1C shows the B--B' cutaway of the same.
As shown in FIG. 1B, a memory cell transistor comprises an N.sup.+ type source diffusion area 5 and an N.sup.+ type drain diffusion area 4 on the surface of a P type Si (silicon) substrate 1. On top of its channel formed between the N.sup.+ type source diffusion area 5 and the N.sup.+ type drain diffusion area 4, it has a layered structure comprising an insulation film 6, a floating gate 2 made of polysilicon, another insulation film 6 and a control gate 3. Therefore, the capacitance of the floating gate 2 and that of the control gate 3 are coupled through such an insulation film 6.
As such, a memory cell transistor of an EPROM has a structure in which a floating gate is attached under a gate of an N-channel MOS transistor (corresponding to the control gate3).
An ultraviolet ray radiation energizes electrons stored in the floating gate 2 of a memory cell transistor having the above structure, which causes the electron to be emitted out of the floating gate 2. As a result, the electrons of the floating gate 2 become void and data are erased.
In this state, a simultaneous application of a high voltage to the control gate 3 and the N.sup.+ type drain diffusion area 4 causes an avalanche breakdown phenomenon near the N.sup.+ type drain diffusion area 4 of the channel. The floating gate 2 captures some of the hot electrons charged with high energy near the N.sup.+ type drain diffusion area 4.
The electrons consequentially stored in the floating gate 2 raise the threshold voltage of the memory cell transistor controlled by the control gate 3. This prevents the memory cell transistor from becoming conductive despite an application of a proper readout voltage, such as five volts [5V], to the control gate 3, thereby preventing a datum from being written in erroneously.
Meanwhile, since the floating gate 2 does not store electrons when data have been erased, an application of the proper readout voltage, such as five volts [5V], to the control gate 3 causes the memory cell transistor to become conductive. A further application of another predetermined voltage, such as one volt [1V], to the N.sup.+ type drain diffusion area 4 causes the readout current to flow in the memory cell transistor.
Thus, the correspondence between the ON (conductance) and OFF (non-conductance) states of the memory cell transistor and the binary data comprising zero [0] and one [1] enables the memory cell transistor to store the binary data.
FIGS. 2A, 2B and 2C are a block diagram and circuit diagrams of an EPROM with a redundancy ROM.
FIG. 2A schematically shows an example of the entire configuration of a conventional semiconductor memory device.
An actual EPROM arrays a plurality of memory cell transistors, such as ones shown in FIG. 1, in a matrix form.
In FIG. 2A, a memory cell array 11 comprises a predetermined number of memory cell transistors T.sub.00, T.sub.01, . . . ; T.sub.10, T.sub.11, . . . ; and T.sub.n0, T.sub.n1, . . . , among which memory cell transistors T.sub.n0, T.sub.n1, . . . form redundant circuits.
A row address buffer 12 outputs to a row decoder 13 internal row address signals A0, A0, A1, A1, . . . , and Am, Am by reshaping the waveform of and inverting the inputted row address signals A0 through Am.
The row decoder 13 selects an appropriate word line, e.g. WL.sub.0, determined by the above internal row address signals upon their receipt. It sets the voltage of the selected word line, which is WL.sub.0, to a high level and sets those of all other unselected word lines, which are designated as WL.sub.1 through WL.sub.n, to a low level, for example.
Among the above described (n+1) word lines WL.sub.0, WL.sub.1, . . . , and WL.sub.n, word line WL.sub.n is connected to the output side of a match detecting circuit 19 and is selected by an output from the match detecting circuit 19.
A write-in direct current power source V.sub.pp sets selected word lines WL.sub.0, WL.sub.1, . . . e.g. to twelve point five volts [12.5V] when data are written, while a readout direct current power source V.sub.cc sets them e.g. to five volts [5V] when data are read.
Each of the word lines WL.sub.i (i=0, 1, . . . , and n) is connected to the control gate 3 of a corresponding one of the above plurality of memory cell transistors T.sub.i0, T.sub.i1, . . .
A column address buffer 22 outputs to a column decoder 23 internal column address signals An, . . . , and Ap, Ap by reshaping the waveform of and inverting the inputted column address signals An through Ap.
The column decoder 23 selects an appropriate bit line, e.g. BL.sub.0, determined by the above internal column address signals upon their receipt. It sets the gate voltage of a transfer gate transistor, e.g. TS.sub.0, connected to the selected bit line, which is BL.sub.0, to a high level and sets that of another transfer gate transistor, e.g. TS.sub.1, connected to the other unselected bit line, which is designated as BL.sub.1, to a low level, for example.
Also, the control gate 3 of each of the memory cell transistors T.sub.00, T.sub.01, . . . ; T.sub.n0, T.sub.n1, . . . of the memory cell array 11 is connected to the corresponding one of the word lines WL.sub.0 through WL.sub.n. The floating gate 2 of each of the memory cell transistors T.sub.00, T.sub.01, . . . ; T.sub.n0, T.sub.n1, . . . of the memory cell array 11 is surrounded by the corresponding insulation film 6 shown in FIG. 2A.
When a datum "zero [0]" is written into a particular memory cell transistor T.sub.00, the column decoder 23 selects bit line BL.sub.0, the row decoder 13 selects word line WL.sub.0, and the write-in direct current power source V.sub.pp applies its high voltage, which is twelve point five volts [12.5V] in this example, to the control gate 3 of memory cell transistor T.sub.00. Also, at this time, a write-in circuit 15 energizes memory cell transistor T.sub.00 by setting the voltage on its output side to a high level (e.g. between seven volts [7V] and eight volts [8V] on receiving a write-in datum (e.g. "zero [0]") through a data input buffer 14. The floating gate 2 of memory cell transistor T.sub.00 stores hot electrons charged with high energy generated by the avalanche breakdown phenomenon near the N.sup.+ type drain diffusion area 4. Memory cell transistor T.sub.00 to which the write-in datum (e.g. "zero [0]") is thus written does not allow a current to flow, even if the readout direct current power source V.sub.cc applies the predetermined readout voltage, which is five volts [5V] in this example, to the control gate 3 through word line WL.sub.0 when its datum is read.
Consequently, memory cell transistor T.sub.00 allows its stored datum ("zero [0]" in this example) to be read by having a sense amplifier 16 and a data output buffer 17 detect its non-conductive state.
Meanwhile, when the datum "one [1]" is written in a predetermined memory cell transistor (e.g. T.sub.00), the write-in circuit 15 puts its output side in an electrically floating state. When a datum is written, memory cell transistor T.sub.00 is not energized and its floating gate 2 stores no electron.
Therefore, memory cell transistor T.sub.00 to which the datum "one [1]" is written is energized by applying the above predetermined readout voltage to its control gate 3 through word line WL.sub.0 when its datum is read. Also, at this moment, an application of a predetermined voltage (e.g. two volts [2V]) to its N.sup.+ type drain diffusion area 4 through bit line BL.sub.0 causes a predetermined readout current to flow in memory cell transistor T.sub.00. As such, the datum "one [1]" stored in memory cell transistor T.sub.00 is read out by having the sense amplifier 16 connected to bit line BL.sub.0 output a detection of a voltage fall caused by the readout current.
Also, a redundancy ROM 18 stores the address signal corresponding to the address of a bad cell in the memory cell array 11 (which is the row address of the bad cell in this case) and outputs the address signal to the match detecting circuit 19.
The match detecting circuit 19 selects word line WL.sub.n and halts the operation of the row decoder 13, when the row address buffer 12 outputs the row address signal corresponding to the address of a bad cell.
FIGS. 2B and 2C are circuit diagrams showing the exemplary internal configuration of the redundancy ROM 18.
More specifically, FIG. 2B shows the circuit configuration of a fuse ROM having a fuse 18a made of polysilicon. Ordinarily, a transistor 18c receives at its gate a gate signal Sc at a low level, remains non-conductive, and its output signal (ROM signal) from OUT on the output side is at a high level, i.e. a datum being "one [1]". When the gate signal Sc is at a high level, (i.e. when a severance signal is supplied,) transistor 18c is energized and the fuse 18a is dissolved by heat. Then, a pull-down resistor 18b causes the output signal from OUT on the output side to be at a low level, i.e. a datum being "zero [0]". By providing fuse ROMs having such a circuit configuration in the number of bits of the row addresses, the address of a bad cell is memorized. Yet, a destruction type memory device utilizing a heat dissolution of a fuse has the disadvantage of low reliability due to a possible reconnection of the dissolved fuse.
FIG. 2C shows the circuit configuration of a redundancy ROM comprising a transistor with a floating gate recently used as a memory cell of an EPROM.
In this case, a receipt at its gate of five volts [5V] from the readout direct current power source V.sub.cc energizes a transistor 18d, and the signal from OUT on its output side is at a low level, i.e. a datum being "zero [0]". An application of the gate signal Sc at a high voltage (e.g. twelve point five volts [12.5V]) to the gate of transistor 18d causes its floating gate to store electrons, thereby making it non-conductive. A pull-up resistor 18e causes the output signal from OUT on the output side to be at a high level, i.e. a datum being "one [1]".
A use of such a non-destruction type memory element enables a highly reliable redundancy ROM to be structured.
Generally, a semiconductor memory device such as an EPROM erases its data written on its memory cell array in the body of the EPROM. In doing so, it eliminates electrons stored in the floating gate of a memory cell transistor. A radiation of strong ultraviolet rays over an entire chip through the upper side of a silicon dioxide surface allows the electrons to be discharged.
However, when data written in the memory cell array are erased in this manner, it is necessary to avoid erasing, by the strong irradiated ultraviolet ray, data (indicating the address of a bad cell) written in the memory cell transistor (such as transistor 18d shown in FIG. 2C) forming the redundancy ROM 18. Thus, conventionally, so as to prevent the ultraviolet ray from erasing data stored in the redundancy ROM, the surface of a memory cell transistor, i.e. the insulation film 6, forming the redundancy ROM is covered with shield coating 35 e.g. made of aluminum, as shown in FIG. 3A.
Next, FIGS. 3A and 3B are referred to in explaining the configuration of a memory cell transistor of a conventional redundancy ROM 18.
Parts shown in FIGS. 3A and 3B which are identical to those shown in other drawings have the same numbers.
FIG. 3A shows the A--A' cutaway of a memory cell transistor of a conventional redundancy ROM.
In FIG. 3A, the N.sup.+ type drain diffusion area 4, the N.sup.+ type source diffusion area 5, the floating gate 2 and the control gate 3 on top of the P type silicon substrate 1 form an EPROM transistor in a redundancy ROM 18. An N.sup.- type union conductive well 31 ordinarily formed in a CMOS type integrated circuit is used to electrically connect the N.sup.+ type drain diffusion area 4 with an N.sup.+ type diffusion area 32, which is for drain terminal connection. Further, a drain terminal 36 is formed of aluminum. A P.sup.+ type diffusion area 33 in the N.sup.- type union conductive well 31 is provided between the N.sup.+ type drain diffusion area 4 and the N.sup.+ type diffusion area 32, which is for drain terminal connection. The P.sup.+ type diffusion area 33 is connected to an edge of the shield coating 35.
A field oxide surface and a PSG (Phospho-Silicate Glass) surface on the P type silicon substrate 1 form the insulation film 6. A contact part 35b of the shield coating 35 made of aluminum is connected to the N.sup.+ type source diffusion area 5 to function as a source terminal. Another contact part 35a of the shield coating 35 on the left hand side is connected to the P.sup.+ type diffusion area 33 provided in the N.sup.- type union conductive well 31. With such a connecting configuration, the shield coating 35 completely shields the memory cell transistors in the redundancy ROM 18, thereby enabling the contact part 35a to prevent the ultraviolet ray (shown as UV in FIG. 3A) irradiating the body of the EPROM from spilling over to the inside of the memory cell transistors.
The area covered by the shield coating 35 in a memory cell transistor of the redundancy ROM 18 having the above configuration need not be too large. The distance extending to the left hand side of the N.sup.+ type source diffusion area 5 need only be about a few tens of microns. Meanwhile, the N.sup.- type union conductive well 31 electrically connects the N.sup.+ type drain diffusion area 4 with the N.sup.+ type diffusion area 32 for drain terminal connection, thereby forming an electric link from the drain terminal 36 to the N.sup.+ type drain diffusion area 4. A source terminal 35c in the shield coating 35 in the memory cell transistor shown in FIGS. 3A and 3B is connected to the P.sup.+ type diffusion area 34 for contacting, thereby covering the surface of the P type silicon substrate 1 and the shield coating 35.
FIG. 3B is a top view of the memory cell transistor shown in FIG. 3A.
As described above, the P type silicon substrate 1 of the memory cell transistor touches, in the N.sup.- type union conductive well 31, the contact part 35a of the shield coating 35. It also touches, in the P.sup.+ type diffusion area 33 accompanied by the P.sup.+ type diffusion area 34, the shied coating 35 at its left and right sides, except for a lead part D of the control gate 3, of the P type silicon substrate 1 for shield. These are for preventing an ultraviolet ray from entering into the memory cell transistor. Although it is impossible to completely encapsulate the lead part D, the spacing between the control gate 3 and the surface of the P type silicon substrate 1 is extremely small, approximately at a few hundred angstroms. Therefore, the intrusion of an ultraviolet ray through the minimal spacing is almost negligible.
FIG. 4A shows an example of the form of the control gate 3 and the contact part 35a of the shield coating 35, which are illustrated in FIGS. 3A and 3B.
In reality, the contact part 35a in the lead part D is shaped into the form shown in FIG. 4A, and the control gate 3 is three-dimensionally reshaped to match the conclave. Thus, the intrusion of the ultraviolet ray is further restricted to almost nil.
FIG. 4B shows an equivalent circuit of an EPROM memory cell.
A predetermined voltage is applied to the drain terminal 36. The N.sup.+ type source diffusion area 5 is connected to the ground terminal. The N.sup.- type union conductive well 31 forms a drain parasitic resistance between the drain terminal 36 and the N.sup.+ type drain diffusion area 4.
The width of the N.sup.- type union conductive well 31 constrains the miniaturization of the redundancy ROM 18 conventionally configured as shown in FIG. 3. That is, the redundancy ROM 18 causes the N.sup.- type union conductive well 31 to connect the N.sup.+ type drain diffusion area 4 of a memory cell transistor with an external terminal, so as to prevent an undesirable intrusion of an ultraviolet ray into the memory cell transistor. However, when the ratio of impurities in the N.sup.- type union conductive well 31 is relatively low, the parasitic resistance to the N.sup.- type union conductive well 31 is large and it is feared that the voltage applied to the edge of the N.sup.+ type drain diffusion area 4 of the memory cell transistor falls.
For instance, when the voltage applied to the edge of the N.sup.+ type drain diffusion area 4 falls significantly, a write-in to the memory cell transistor is not conducted effectively. Therefore, so as to inhibit the voltage applied to the edge of the N.sup.+ type drain diffusion area 4 from falling and the parasitic resistance to the edge of the N.sup.+ type drain diffusion area 4 from rising, the N.sup.- type union conductive well 31 must be ensured to have a sufficient width. However, this prevents the redundancy ROM 18 from being miniaturized.
The problem of a difficulty in miniaturizing the redundancy ROM 18 becomes more critical in reducing the overall dimensions of a semiconductor memory device, because the differences in the dimensions of a memory cell array and those of a memory cell transistor become more apparent as the memory becomes more highly integrated.